1. Technical Field
The present invention relates generally to an apparatus for interfacing between a central processing unit (CPU) and a main memory unit and, more particularly, to an apparatus for interfacing between a CPU and a main memory unit, whereby data is transmitted between the CPU and the main memory unit by using optical signals; and a method for interfacing between a CPU and a main memory unit using the same.
2. Description of the Related Art
As well known to those skilled in the art, a system based on a microprocessor identified as a central processing unit (CPU), such as a computer system or a communication system, requires a large number of main memory units 20 that are capable of performing a high-speed operation for data processing.
FIG. 1 is a view of a configuration of an apparatus for interfacing between a CPU 10 and a main memory unit 20 according to the related art. In general, the CPU 10 may include one to eight cores 11, and in FIG. 1, the CPU 10 includes four cores 11.
The CPU 10 includes a plurality of cores 11 that perform an arithmetic operation. In this case, each of the plurality of cores 11 is connected to an individual cache memory unit 12.
The individual cache memory unit 12 is interfaced with a shared cache memory unit 13, and since the number of cores 11 of the CPU 10 is four, the number of interfaces between the individual cache memory unit 12 and the shared cache memory unit 13 is four.
The shared cache memory unit 13 is interfaced with the main memory unit 20 by using a memory controller 14 and transmits/receives data to/from the main memory unit 20. The shared cache memory unit 13 transmits/receives data to/from a peripheral device, for example, an auxiliary memory unit or an input/output unit, by using a peripheral device input/output controller 15.
In the related art, memory using a double data rate (DDR) method is mainly used as the main memory unit 20 for large-capacity and high-speed processing. The memory used as the main memory unit 20 selects an interface having a signal transmission line of 32-bit or 64-bit, in terms of a data width, as an interface with the memory controller 14 embedded in a CPU for a high-speed operation.
Also, the memory used as the main memory unit 20 is connected to an interface having a signal transmission line of 40-bit or more for address and control information and thus requires 100 or more signal transmission lines. In this case, since the signal transmission lines require a high-speed operation, an operation of 400 MHz is required in the oldest version using the DDR method, and DDR4 that is currently standardized and the latest DDR method requires a high-speed operation up to 3200 MHz.
A coupling shape of the memory controller 14 and the main memory unit 20 is referred to as a channel, and in an initial DDR method, four memories can be coupled to each channel, but in the latest high-speed DDR method, only one memory can be coupled to each channel.
Since the amount of memory required for high-performance computing, such as a need for current big data processing, is enormously increased, in the related art, there are attempts for increasing available memory by adopting a method of increasing the capacity of the main memory unit 20 itself or increasing the number of channels.
However, there is a limitation in increasing the capacity of memory, because a process does not make advance any more according to Moore's Law and Hwang's Law based on development in process.
In addition, increasing the number of channels has also a limitation in the size of a die, because the number of interfaces between the memory controller 14 and the main memory unit 20 is large, as described above.
In addition, since signal transmission lines between the memory controller 14 and the main memory unit 20 should be disposed as close as possible due to crosstalk in each signal transmission line and the amount of power consumption, due to the size of the CPU 10 and the size of the main memory unit 20, as the number of channels is increased, there is a limitation in disposing several channels to be close to one another such that only two or three channels can be expanded at the present point in time.
In this way, since there is a limitation in increasing the capacity of memory per main memory unit 20, in order to fundamentally solve this limitation, a method of increasing the number of channels of the CPU 10 by reducing the number of signal transmission lines itself without any limitation is most preferable.
FIG. 2 is a view of the apparatus for interfacing between the memory controller 14 and the main memory unit 20 illustrated in FIG. 1 according to the related art, so as to reduce the number of signal transmission lines. In FIG. 2, an electrical-to-optical (E/O) converter 40 is disposed in the middle of the memory controller 14 and the main memory unit 20 instead of directly connecting the memory controller 14 and the main memory unit 20. Thus, electrical signals are transmitted between the memory controller 14 and the E/O converter 40 instead of directly transmitting/receiving electrical signals. In this case, optical signals are transmitted between two E/O converters 40, and electrical signals are transmitted between the E/O converter 40 and the main memory unit 20. Thus, a limitation in arrangement that occurs due to the size of the CPU 10 and the main memory unit 20, among the above-mentioned limitations can be solved. However, a difficulty in increasing the number of channels that occurs due to the die size of the main memory unit 10 is not solved yet.
FIG. 3 is a view of the apparatus for interfacing between the memory controller 14 and the main memory unit 20 illustrated in FIG. 1 according to the related art, so as to reduce the number of signal transmission lines. An E/O converter 16 of the CPU 10 illustrated in FIG. 3 converts signal transmission lines that are generated in the memory controller 14 into optical signals (E/O), and an optical multiplexing unit (OMUX) 17 multiplexes the optical signals and transmits the multiplexed optical signals to the main memory unit 20. Thus, an OMUX unit 21 of the main memory unit 20 separates the multiplexed optical signals received from the CPU 10 from the signal transmission lines connected to a memory cell 23, and an optical-to-electrical (O/E) converter 22 converts the optical signals into electrical signals (O/E) and transmits the optical signals into the memory cell 23.
The main memory unit 20 converts signal transmission lines generated in the memory cell 23 into optical signals by using an E/O converter 24 and multiplexes the optical signals and transmits the multiplexed optical signals to the memory controller 14 by using an OMUX unit 25. Thus, an OMUX unit 18 of the CPU 10 separates the multiplexed optical signals received from the main memory unit 20 from the signal transmission lines connected to the memory controller 14, and an O/E converter 19 converts the optical signals into electrical signals and transmits the optical signals to the memory controller 14. In this case, since 100 or more signal transmission lines of the memory controller 14 are present, 100 or more E/O converters 16 and 24 or O/E converters 19 and 22 are required to convert signals of the signal transmission lines into optical signals such that there is a limitation in the area of the CPU 10. Since there is a limitation in multiplexing 100 optical signals in current technology, it is difficult to implement this multiplexing, and there is a limitation in applying this multiplexing to current high-speed memory.
Also, since the number of signal transmission lines is large, problems may occur in data transmission/reception due to skew that occurs in the signal transmission lines. However, since no method of aligning signal transmission lines is present in the above related art, precise measurement and implementation is required in a board not to be affected by an operational environment, and the length of optical signal transmission lines is limited.
Optical communication has been already applied to communication equipment so as to correspond to an increase in a data amount and high-speed. In optical communications used in communication equipment, skew compensation between signal transmission lines is possible, and safe data transmission/reception is guaranteed.
Thus, in order to overcome the above-described limitations in interfacing between the memory controller 14 and the main memory unit 20, it is preferable to apply algorithms used in communication.
However, optical communication used in the communication equipment is limited to communication protocols and is not designed to be suitable for access to memory and has many delay times and thus cannot be applied to memory access that requires a fast response time. In connection with this, Korean Patent Publication No. 10-2012-0027209 discloses a technology related to “Optical Memory Expansion” and Korean Patent Publication No. 10-2013-0028563 discloses a technology related to “Optical Connection Apparatus, Method of Manufacturing the Same, and Memory System including the Optical Connection Apparatus”